The SiT95210 clock generator offers programmable quad fractional frequency translation-based jitter cleaning with flexible input to output frequency translation options. The ultra-high performance PLLs support up to 4 differential or 8 single-ended input clocks that are common for all 4 fractional translations and provide 4 clock outputs. The clock outputs can be derived from any of the 4 PLLs in a fully flexible manner. This device is fully programmable with the I2C/SPI interface or an on-chip one-time programmable (OTP) non-volatile memory for factory pre-programmed devices.
"Specs" | "Value" |
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Operating Temperature Range (°C) | -40 to 85 |
Package Type (mm²) | 7x7 mm, 44-pin QFN |
Number of Inputs | 4 |
Number of Outputs | 4 |
Input Type | LVCMOS, LVDS, LVPECL, CML |
Input Frequency Range | 200 kHz to 2.1 GHz (Differential) |
Output Type | LVPECL, CML, HCSL, LVDS, LVCMOS |
Output Frequency Range | 0.5 Hz to 2.94912 GHz (Differential) |
Number of PLL/Clock Domains | 4 PLL |
Phase Jitter (rms) | 85 fs typ.; 70 fs typ. (with MEMS oscillator) |
Repeatable Input-Output Delay | ±225 ps |
Frequency Control DCO | 0.001 ppt (all outputs) |
Phase Control DCO | <1 ps (all outputs) |
Internal ZDB Mode | <0.5 ns input to output delay variation |
Programmability | NVM OTP, External EEPROM, Partial autonomous, SPI/I2C |
Availability | Production |
44-pin 7x7 mm QFN Clock Generators - Network Synchronizers - Jitter Cleaners package
SiT95210 Evaluation Board HW User Manual – Configure and evaluate device performance
Setup SiTGUI 3.6 – Download software .exe file
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